1 . Field of the Invention
The present invention relates to an antifuse programming circuit of a semiconductor memory device.
2 . Description of the Related Art
In semiconductor memory devices, a method for improving yield is conventionally employed in which memory cells that are defective due to faults are replaced by spare memory cells.
As one example of this type of method, a technique has been proposed in which high voltage is applied from the outside to program (destroy) antifuses, as shown in FIG. 1 (for example, refer to 2000 IEEE International Solid-State Circuits Conference, ISSCC 2000/Session 24/DRAM/Paper WP 24.8, pp. 406–407). Alternatively, as shown in FIG. 2, methods have been proposed in which the applied voltage is a negative voltage that is generated inside (for example, refer to 2001 Symposium on VLSI Circuits, Digest of Technical Papers, “A Post-Package Bit-Repair Scheme Using Static Latches with Bipolar-Voltage Programmable Antifuse Circuits for High-Density DRAMs,” pp. 67–68).
In FIG. 1, during programming, node VPRG is at a high voltage VPP that is equal to or greater than VDD, and selection signal SEL is applied to the gate of transistor M21. At this time, node Lo of antifuse AF that has been selected by transistor M21 is at VSS, and antifuse AF is thus programmed. Node N3 of antifuse that is not selected is VDD because transistor M21 is OFF. At levels equal to or greater than VDD−VTN, NMOS M26 turns OFF and programming therefore does not occur. In addition, in antifuse AF that is programmed and conductive at both ends, NMOS M26 remains OFF even when node Lo is at level VPP, and a leakage current therefore does not flow. Essentially, PMOS M25 has the functions of charging the Lo node of an undestroyed antifuse to VPP−VTN and relaxing the voltage differential at the two ends of the antifuse, and NMOS M26 has a blocking function such that leakage current does not flow by way of an already destroyed antifuse.
FIG. 2 corresponds to a case in which the polarity in FIG. 1 is reversed.
In Japanese Patent Laid-Open Publication No. 2001-243787 (Page 1, FIG. 1), a technique is disclosed in which, in a programming circuit in which a negative voltage is applied, the output terminal of a negative voltage generation means is connected to the ground terminal.
In order to program an antifuse, it is necessary to apply high voltage and cause current to flow. In the above-described prior art, two stages of transistors are interposed in a series with the antifuse between the two terminals of the power supply when programming (NMOS M21 and NMOS M26 in FIG. 1, and NMOS M33 and MNOS M38 in FIG. 2). Thus, if a drop in voltage is to be suppressed and the current capacity secured, the area that is occupied by the transistors becomes great.
In the prior-art example that is shown in FIG. 1, eliminating NMOS M26 to leave just one transistor means that when node Lo (N3) becomes VPRG, PMOS M25 that is connected to VDD will not turn OFF and a leakage current will flow between VPRG-VDD. As a result, with the progression of programming of the multiplicity of antifuses that exist on a chip, the voltage of VPP (VPRG) will drop and the applied voltage and current will therefore also drop, preventing the stable programming of antifuses.